# 这数电实验做的我要吐了

## 实验1：五输入表决器设计

#### 源码

module first(K,m_Result);
input[5:1] K;
output m_Result;
integer i;
reg m_Result;
reg[2:0] sum;
always@(K)
begin
sum=0;
for(i=1;i<=5;i=i+1)
if(K[i]) sum=sum+1;
if(sum>=3) m_Result=1;
else m_Result=0;
end
endmodule


#### 测试代码

module test;

// Inputs
reg [5:1] K;

// Outputs
wire m_Result;

// Instantiate the Unit Under Test (UUT)
first uut (
.K(K),
.m_Result(m_Result)
);

initial begin
// Initialize Inputs
K = 0;

// Wait 100 ns for global reset to finish
#100;

#100;
K[0]=0;K[1]=1;K[2]=1;K[3]=0;K[4]=0;

#100;
K[0]=0;K[1]=1;K[2]=1;K[3]=0;K[4]=1;

#100;
K[0]=1;K[1]=1;K[2]=1;K[3]=1;K[4]=1;

#100;
K[0]=1;K[1]=1;K[2]=0;K[3]=0;K[4]=0;
end

endmodule


## 实验2：多路数据选择器设计

#### 源码

module second(sel,in1,in0,en,out);
input[1:0] sel;
input[3:0] in1,in0;
input en;
output reg[1:0] out;
always@(sel && !en) begin
if(!en) begin
case({sel[1],sel[0]})
2'b00: begin out[1]=in1[0];out[0]=in0[0]; end
2'b01: begin out[1]=in1[1];out[0]=in0[1]; end
2'b10: begin out[1]=in1[2];out[0]=in0[2]; end
2'b11: begin out[1]=in1[3];out[0]=in0[3]; end
default:begin out[1]=0;out[0]=0; end
endcase
end
else begin out[1]=0;out[0]=0; end
end
endmodule


#### 测试代码

module test2;

// Inputs
reg [1:0] sel;
reg [3:0] in1;
reg [3:0] in0;
reg en;

// Outputs
wire [1:0] out;

// Instantiate the Unit Under Test (UUT)
second uut (
.sel(sel),
.in1(in1),
.in0(in0),
.en(en),
.out(out)
);

initial begin
// Initialize Inputs
sel = 0;
in1 = 0;
in0 = 0;
en = 0;

// Wait 100 ns for global reset to finish
#100;

#100;
en=1;

#100;
en=0;
in1[0]=1;in0[0]=1;
in1[1]=1;in0[1]=0;
in1[2]=0;in0[2]=1;
in1[3]=0;in0[3]=0;
sel[0]=0;sel[1]=1;

#100;
en=0;
in1[0]=1;in0[0]=1;
in1[1]=1;in0[1]=0;
in1[2]=0;in0[2]=1;
in1[3]=0;in0[3]=0;
sel[0]=0;sel[1]=0;

#100;
en=0;
in1[0]=1;in0[0]=1;
in1[1]=1;in0[1]=0;
in1[2]=0;in0[2]=1;
in1[3]=0;in0[3]=0;
sel[0]=1;sel[1]=1;

#100;
en=1;
in1[0]=1;in0[0]=1;
in1[1]=1;in0[1]=0;
in1[2]=0;in0[2]=1;
in1[3]=0;in0[3]=0;
sel[0]=0;sel[1]=1;

#100;
en=0;
in1[0]=1;in0[0]=1;
in1[1]=1;in0[1]=0;
in1[2]=0;in0[2]=1;
in1[3]=0;in0[3]=0;
sel[0]=0;sel[1]=0;

end

endmodule


## 实验5：数值比较器设计

#### 源码

module five(
input wire[3:0] a,
input wire[3:0] b,
output reg[2:0] y
);
always@(a or b) begin
if(a>b) y<=3'b011;
if(a==b) y<=3'b101;
if(a<b) y<=3'b110;
end
endmodule


#### 测试程序

module test5;

// Inputs
reg [3:0] a;
reg [3:0] b;

// Outputs
wire [2:0] y;

// Instantiate the Unit Under Test (UUT)
five uut (
.a(a),
.b(b),
.y(y)
);

initial begin
// Initialize Inputs
a = 0;
b = 0;

// Wait 100 ns for global reset to finish
#100;

#100;
a=4'b0011;b=4'b1010;

#100;
a=4'b1110;b=4'b1110;

#100;
a=4'b1010;b=4'b1010;

#100;
a=4'b1110;b=4'b0010;
end

endmodule



## 实验8:RS触发器

module RS(q,qb,r,s,clk);
output q,qb;
input r,s,clk;
reg q;
assign qb=~q;
always @(posedge clk)
case({r,s})
2'b01:q<=1'b1;
2'b10:q<=1'b0;
2'b11:q<=1'bx;
endcase
endmodule


#### 测试程序

module tt8;

// Inputs
reg r;
reg s;
reg clk;

// Outputs
wire q;
wire qb;

// Instantiate the Unit Under Test (UUT)
RS uut (
.q(q),
.qb(qb),
.r(r),
.s(s),
.clk(clk)
);

initial begin
// Initialize Inputs
r = 0;
s = 0;
clk = 0;

// Wait 100 ns for global reset to finish
#10;
r = 0;
s = 0;
#20;
r = 0;
s = 1;
#40;
r = 1;
s = 0;
#60;
r = 1;
s = 1;
end
always #10 clk = ~clk;

endmodule


## 实验9:D触发器

module D(r,s,cp,d,q,qn);
input r;
input s;
input cp;
input d;
output q;
output qn;
reg q;
reg qn;
always@(posedge cp)
begin
if({r,s}==2'b01)
begin
q <= 1'b0;
qn <= 1'b1;
end
else if({r,s}==2'b10)
begin
q <= 1'b1;
qn <= 1'b0;
end
else if({r,s}==2'b11)
begin
q <= d;
qn <= ~d;
end
end
endmodule


#### 测试程序

module tt9;

// Inputs
reg r;
reg s;
reg cp;
reg d;

// Outputs
wire q;
wire qn;

// Instantiate the Unit Under Test (UUT)
D uut (
.r(r),
.s(s),
.cp(cp),
.d(d),
.q(q),
.qn(qn)
);

initial begin
// Initialize Inputs
r = 0;
s = 0;
cp = 0;
d = 0;

// Wait 100 ns for global reset to finish
#100;
r=0;s=1;cp=1;d=1;
#100;
r=1;s=1;cp=1;d=1;
#100;
r=1;s=1;cp=0;d=0;
#100;
r=0;s=1;cp=0;d=1;
#100;
r=0;s=1;cp=1;d=0;
#100;
r=0;s=0;cp=1;d=1;

end

endmodule


## 实验10:JK触发器

module jk(input J,input K,input clk,input rst_n,output reg Q);
always @(posedge clk or negedge rst_n)
if(!rst_n) Q <= 1'b0;
else
case({J,K})
2'b00: Q <= Q;
2'b01: Q <= 0;
2'b10: Q <= 1;
2'b11: Q <= ~Q;
endcase
endmodule



#### 测试程序

module tt10;

// Inputs
reg J;
reg K;
reg clk;
reg rst_n;

// Outputs
wire Q;

// Instantiate the Unit Under Test (UUT)
jk uut (
.J(J),
.K(K),
.clk(clk),
.rst_n(rst_n),
.Q(Q)
);

initial begin
clk = 0;
rst_n = 1;
#10;
J = 0;
K = 0;
#10;
J = 0;
K = 1;
#10;
J = 1;
K = 0;
#10;
J = 1;
K = 1;
end
always #10 clk = ~clk;
endmodule



## 实验11:同步二进制计数器设计

module counter2(q,cout,r,clk);
output[3:0] q;
output cout;
input r,clk;
reg[3:0] q;
reg cout;
always @(posedge clk)
begin q=q+1;
if(r) q=4'b00;
else if(q==4'b1111)
cout=cout+1;
else cout=cout;
end
endmodule


#### 测试程序

module t11;

// Inputs
reg r;
reg clk;

// Outputs
wire [3:0] q;
wire cout;

// Instantiate the Unit Under Test (UUT)
counter2 uut (
.q(q),
.cout(cout),
.r(r),
.clk(clk)
);

initial begin
// Initialize Inputs
r = 0;
clk = 0;

// Wait 100 ns for global reset to finish
forever#20 clk = ~clk;

end
initial begin
#30 begin
r=1;
end
#200 begin
r=1;
end
#345 begin
r=0;
end
end

endmodule


## 实验12:十进制计数器设计

module cnt10(clk_k,clk,clr,ena,sum,cout);
input clk,clk_k,clr,ena;
output[3:0] sum;
output cout;
reg[3:0] sum;
reg cout;
reg a,b;
always @(posedge clk )
begin a <= clk_k;
b = a;
end
wire key_posedge = (~b&a)?1'b1:1'b0;
always @(posedge clk)
begin
if(clr)
begin
cout<= 0;
sum <= 0;
end
else if(key_posedge&ena)
begin
if(sum < 4'd9)
begin
sum <= sum+1'b1;
cout<= 0;
end
else
begin
cout<= 1;
sum <= 0;
end
end
else
begin
cout<= cout;
sum <= sum;
end
end
endmodule


#### 测试程序

module t5;

// Inputs
reg clk_k;
reg clk;
reg clr;
reg ena;

// Outputs
wire [3:0] sum;
wire cout;

// Instantiate the Unit Under Test (UUT)
cnt10 uut (
.clk_k(clk_k),
.clk(clk),
.clr(clr),
.ena(ena),
.sum(sum),
.cout(cout)
);

initial begin
// Initialize Inputs
clk_k = 0;
clk = 0;
clr = 0;
ena = 0;

// Wait 100 ns for global reset to finish
forever#10 clk = ~clk;

end
initial begin
forever#20 clk_k = ~clk_k;
end
initial begin
#30 begin clr = 1;
ena= 0;
end
#30 begin clr = 1;
ena = 1;
end
#30 begin clr = 0;
ena = 1;
end
end

endmodule



## 实验13:4位可逆计数器设计

module counter(clk,clr,s,en,updn,data_out);
input clk,clr,s,en,updn;
output [3:0] data_out;
reg [3:0] data_out;
always @ (posedge clk )
if(clr) begin
data_out<=0;
end
else
if(s) begin
data_out<=1;
end
else
if(en) begin
if(updn) begin
if(data_out==15)
data_out<=0;
else
data_out<=data_out+1;
end
else begin
if(data_out==0)
data_out<=15;
else
data_out<=data_out-1;
end
end
else
data_out<=data_out;
endmodule


#### 测试程序

module tt14;

// Inputs
reg clk;
reg clr;
reg s;
reg en;
reg updn;

// Outputs
wire [3:0] data_out;

// Instantiate the Unit Under Test (UUT)
counter uut (
.clk(clk),
.clr(clr),
.s(s),
.en(en),
.updn(updn),
.data_out(data_out)
);

initial begin
// Initialize Inputs
clk = 0;
clr = 1;
s = 0;
en = 0;
updn = 0;
#10 clr=1;
#10 en=1;
#15 clr=0;
#100 updn=1;
end
always begin
#2 clk = ~clk;
end

endmodule


## 实验14:基本寄存器设计

module shift4(clr,clk,DOUT,D);
input clr ;
wire clr ;
input clk ;
wire clk ;
input [3:0] D ;
wire [3:0] D ;
output [3:0] DOUT ;
reg [3:0] DOUT ;
always @ ( posedge clk or posedge clr)
begin
if (clr==1) DOUT <= 0;
else DOUT <= D ;
end
endmodule


#### 测试代码

module tt1;
// Inputs
reg clr;
reg clk;
reg [3:0] d;

// Outputs
wire [3:0] q;

// Instantiate the Unit Under Test (UUT)
register uut (
.clr(clr),
.clk(clk),
.d(d),
.q(q)
);

initial begin
// Initialize Inputs
clr = 0;
clk = 0;
d = 4'b0001;
end
always begin
#3 clk = ~clk;
#5 d = d + 4'b0001;
end

endmodule


## 实验15:4位移位寄存器设计

module ShiftRegister(q3,data_in,clk,clr);

output[3:0] q3;
input[3:0] data_in;
input clk;
input clr;
reg[3:0] q3,q2,q1,q0;
always@(posedge clk or posedge clr)
if (clr == 1)
begin
q3 <= 0;
q2 <= 0;
q1 <= 0;
q0 <= 0;
end
else
begin
q3<=q2;
q2<=q1;
q1<=q0;
q0<=data_in;
end
endmodule



#### 测试程序

module test1;

// Inputs
reg [3:0] data_in;
reg clk;
reg clr;

// Outputs
wire [3:0] q3;

// Instantiate the Unit Under Test (UUT)
ShiftRegister uut (
.q3(q3),
.data_in(data_in),
.clk(clk),
.clr(clr)
);

initial begin
// Initialize Inputs
data_in = 4'b0001;
#1 clr = 1'b0;
#1 clk=1'b1;
end
always begin
#3 clk = ~clk;
#5 data_in = data_in + 4'b0001;
end

endmodule


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